1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to the manufacture of spacers for NMOS and PMOS transistors and stressed dielectric layers formed above the transistors.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The reduction of the transistor dimensions, however, entails a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One major problem in this respect is the development of enhanced photolithography and etch strategies to reliably and reproducibly create circuit elements of critical dimensions, such as the gate electrode of the transistors, for a new device generation. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity in combination with a desired channel controllability.
Irrespective of the technological approach used, sophisticated spacer techniques are necessary to create the highly complex dopant profile and to serve as a mask in forming metal silicide regions in the gate electrode and the drain and source regions in a self-aligned fashion. Since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of process techniques concerning the above-identified process steps, it has been proposed to enhance device performance of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length.
In principle, at least two mechanisms may be used, in combination or separately, to increase the mobility of the charge carriers in the channel region. First, the dopant concentration within the channel region may be reduced, thereby reducing scattering events for the charge carriers and thus increasing the conductivity. However, reducing the dopant concentration in the channel region significantly affects the threshold voltage of the transistor device, thereby making a reduction of the dopant concentration a less attractive approach unless other mechanisms are developed to adjust a desired threshold voltage. Second, the lattice structure in the channel region may be modified, for instance by creating tensile or compressive strain, which results in a modified mobility for electrons and holes. For example, creating tensile strain in the channel region increases the mobility of electrons, wherein, depending on the magnitude of the tensile strain, an increase in mobility of up to 20% may be obtained, which in turn directly translates into a corresponding increase in the conductivity. On the other hand, compressive stress in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. Consequently, it has been proposed to introduce, for instance, a silicon/germanium layer or a silicon/carbon layer in or below the channel region to create tensile or compressive stress.
Although the transistor performance may be considerably enhanced by the introduction of stress-creating layers in or below the channel region, significant efforts have to be made to implement the formation of corresponding stress layers into the conventional and well-approved CMOS technique. For instance, additional epitaxial growth techniques have to be developed and implemented into the process flow to form the germanium- or carbon-containing stress layers at appropriate locations in or below the channel region. Hence, process complexity is significantly increased, thereby also increasing production costs and the potential for a reduction in production yield.
Another promising approach is the creation of stress in the insulating layer, which is formed after the formation of the transistor elements to embed the transistors and which receives metal contacts to provide the electrical connection to the drain/source regions and the gate electrode of the transistors. Typically, this insulation layer comprises at least one etch stop layer or liner and a further dielectric layer that may be selectively etched with respect to the etch stop layer or liner. In the following, this insulation layer will be referred to as contact layer and the corresponding etch stop layer will be denoted as contact liner layer. In order to obtain an efficient stress transfer mechanism to the channel region of the transistor for creating strain therein, the contact liner layer, that is located in the vicinity of the channel region, has to be positioned closely to the channel region. In advanced transistor architectures, a triple spacer approach is required in order to achieve the highly complex lateral dopant profile mentioned above.
A conventional approach for the formation of a semiconductor structure including at least an NMOS transistor and a PMOS transistor with a stressed contact liner layer will be explained in more detail with reference to FIGS. 1a-1e. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in a certain manufacturing stage for forming stress-inducing layers above the NMOS transistor 102 and the PMOS transistor 101, which may be formed on a substrate 103 comprising a semiconductor layer 105 and an appropriate buried insulating layer 104 if a silicon-on-insulator (SOI) configuration is considered. For both the transistor elements 101 and 102, a triple spacer structure has been completed, consisting of the spacer elements 106, 107 and 108 and respective liner materials 114, 115, acting as etch stop layer during the formation of the spacer elements 106, 107 and 108.
FIG. 1b illustrates the semiconductor device 100 when exposed to a photolithographic process so as to protect the PMOS transistor 101 with a mask 109 during the following final implantation of N-dopants 110. FIG. 1c schematically illustrates the device 100 when the NMOS transistor 102 is protected and the semiconductor device 100 is exposed to a final implantation of P-dopants 111.
FIG. 1d schematically shows the semiconductor device 100 with self-aligned silicided regions 112 after the implantation of the P and N dopants. The extension of the silicided regions is determined by the width of the spacers 106, 107, 108.
Finally, FIG. 1e schematically shows the deposition of the stressed contact liner layer 113 on the PMOS and NMOS transistors in order to increase the stress in the channel regions.
This conventional approach, however, presents a number of disadvantages in that a significant amount of the stress of the contact liner layer 113 is “absorbed” by the spacers, thereby making conventional triple spacer approaches currently less attractive for creating strain in channel regions of advanced transistors.
In order to overcome the above-mentioned disadvantages due to the triple spacer structure, it has been proposed to remove the outer spacers, which are typically made of silicon nitride, at the same time for both transistor types by using, for example, SiN-to-oxide selective chemistry, such as hot phosphoric acid. The removal of the outer spacer element 106, although advantageous in view of enhancing the stress transfer from the stressed layer 113 and reducing the series resistance of the transistors due to the reduced distance of the silicide regions from the channel regions, may result in severe modifications of other circuit elements. One important circuit element is a substrate diode that is used for sensing applications in advanced SOI devices, for instance in view of the thermal management in complex devices.
For this purpose, the diode characteristic of the substrate diode is used for evaluating the thermal conditions. The substrate diode is typically formed in the substrate below the buried oxide layer by providing an opening in the actual silicon layer in which the transistors are formed, wherein the opening extends through the buried oxide to expose the substrate. In order to provide a high degree of process compatibility with standard CMOS techniques, the diode structure in the substrate and the transistors in the “active” silicon layer are formed in a common process sequence. Hence, a variation in the process flow in view of enhancing transistor performance will also affect the substrate diode. For example, the substrate diode may typically be formed in an N-well, that is, the substrate diode is formed according to the process corresponding to the manufacturing sequence of P-type transistors. The removal of spacer elements at the transistor level for reducing silicide spacing and positioning stressed material closer to the channel region therefore also affects the PN junctions in substrate diode, due to the reduced distance of the respective silicide in the substrate, which may result in significantly different diode characteristics or even a shortage of the diode structure.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.